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Mechanical test to assess reliability of si assembly interaction during flip-chip packaging

Mechanical test to assess reliability of si assembly interaction during flip-chip packaging

Flip-chip packages are produced by an interconnection technique in which the active area of a chip is mounted by various interconnecting materials on a multilayer substrate. While flip-chip technologies have progressed rapidly and are now widely used, they present special reliability concerns. A large thermal expansion mismatch between the chip and the substrate increases the likelihood of fatigue failure in solder joints under cyclic thermal loading. In addition, the thermal mismatch often results in the delamination of interfaces between two materials within the interconnect structure, which eventually leads to mechanical and/or electrical failure of the Integrated Circuit. This mechanical reliability issue worsens with the continuous introduction of dielectric layers with impaired mechanical properties and the substitution of lead alloys by lead-free alloys connections.

In this work, a new testing method to mimic stresses during packaging assembly and in-service is presented. The testing procedure is based on the ability of piezoelectric actuators to reproduce expansions and contractions similar to the ones present in the actual packages. The piezo actuator is glued on top of the sample to be evaluated using an adhesive. Electronic Speckle Pattern Interferometry (ESPI) is applied for non-contact, real-time evaluation of the stress/strain fields. The thickness of the adhesive and the relative position between the piezo actuator and the sample are key parameters to obtain repeatable results.

The experiment has been modeled using finite elements. Modeling results show the ability of the developed technique to reproduce the stress state reached during the packaging process. In addition, the sensitivity of ESPI to detect the presence of cracks in the interconnected structure through changes in the strain fields on the surface of the sample has been demonstrated.

The new methodology has been developed from scratch up to the point where a single parameter called “critical voltage" has been defined as an indicator of the resistance to cracking of the structure due to its sensitivity to differences in materials and architectures. This “critical voltage" is the minimum voltage applied to the piezo actuator attached to a specific sample provoking the cracking in the interconnected structure and can be directly calculated using the strain fields measured with ESPI.

Failure analysis of the tested samples has been performed using FIB confirming the presence of cracks at the specific points detected through ESPI and at no any other site in the tested sample. Cracks start at the bumps used to feed the electrical signal to the chip and propagate through different layers and interfaces in the structures under study. Some experiments performed at the FIB chamber (in-situ testing) show the evolution of the cracks due to the piezo actuators action.

The ability of the technique to test the in-service behavior of materials and structures has been checked through cyclic loading of samples. These experiments confirm that most of the damage appears during the firsts loading cycles, minimizing the probability of in-service failure due to the thermal cycling of the chips.


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